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july 2000 preliminary ML4833 * electronic dimming ballast controller general description the ML4833 is a complete solution for a dimmable or a non-dimmable, high power factor, high efficiency electronic ballast. the bicmos ML4833 contains controllers for boost type power factor correction as well as for a dimming ballast. the ML4833 was designed to minimize the number of external components required to build an electronic ballast. the pfc circuit uses a new, simple pfc topology which requires only one loop for compensation. this system produces a power factor of better than 0.99 with low input current thd. an overvoltage protection comparator inhibits the pfc section in the event of a lamp out or lamp failure condition. the ballast controller section provides for programmable starting sequence with individually adjustable preheat and lamp out-of-socket interrupt times. the ic controls lamp output power through feedback. the ML4833 provides a power down input which reduces power to the lamp, for gfi, end of life, etc. features n complete power factor correction and dimming ballast control in one ic n low distortion, high efficiency continuous boost, peak current sensing pfc section n programmable start scenario for rapid or instant start lamps n lamp current feedback for dimming control n variable frequency dimming and starting n programmable restart for lamp out condition to reduce ballast heating n internal over-temperature shutdown replaces external heat sensor n pfc overvoltage comparator eliminates output runaway due to load removal n low start-up current <0.5ma n power reduction pin for end of life and gfi detectors block diagram 6 r set variable frequency oscillator 7 r t /c t 9 r x /c x pre-heat and interrupt timers control & gating logic 3 pdwn 10 c ramp power factor controller under-voltage and thermal shutdown output drivers 2 pifb 1 peao 18 pvfb/ovp v ref 17 pfc out 15 gnd 11 vcc 16 pgnd 12 out b 13 out a 14 lfb out 5 lamp fb 4 interrupt 8 (* indicates part is end of life as of july 1, 2000) rev. 1.0 10/12/2000
ML4833 2 rev. 1.0 10/12/2000 pin configuration pin# name function pin# name function 1 peao pfc error amplifier output and compensation node. 2 pifb sensing of the inductor current and peak current sense point of the pfc cycle by cycle current limit comparator. 3 pdwn a one volt comparator threshold that switches the operating frequency to the preheat frequency when exceeded. 4 lamp fb inverting input of an error amplifier used to sense (and regulate) lamp arc current. also the input node for dimming control. 5 lfb out output of the lamp current error transconductance amplifier used for lamp current loop compensation. 6r set external resistor which sets oscillator f max , and r(x)/c(x) charging current. 7r t /c t oscillator timing components. pin description 8 interrupt input used for lamp-out detection and restart. a voltage less than 1.25 volts resets the chip and causes a restart after a programmable interval. 9r x /c x sets the timing for the preheat, dimming lockout, and interrupt. 10 c ramp integrated voltage of the error amp out. 11 gnd ground. 12 p gnd power ground for the ic. 13 out b ballast mosfet drive output. 14 out a ballast mosfet drive output. 15 pfc out power factor mosfet drive output. 16 vcc positive supply for the ic. 17 v ref buffered output for the 7.5v voltage reference. 18 pvfb/ovp inverting input to pfc error amplifier and ovp comparator input. ML4833 18-pin dip (p18) peao pifb pdwn lamp fb lfb out r set r t /c t interrupt r x /c x pvfb/ovp v ref vcc pfc out out a out b p gnd gnd c ramp 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 top view ML4833 18-pin soic (s18) pvfb/ovp v ref vcc pfc out out a out b p gnd gnd c ramp peao pifb pdwn lamp fb lfb out r set r t /c t interrupt r x /c x 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 top view
ML4833 rev. 1.0 10/12/2000 3 electrical characteristics unless otherwise specified, r set = 22.1ky, r t = 15.8k w , c t = 1.5nf, c vcc = 1f, v cc = 12.5v. (note 1) parameter conditions min typ max units lamp current amplifier (lamp fb, lfb out) input bias current C0.3 C1.0 a small signal transconductance 35 65 105 w input voltage range C0.3 5.0 v output low voltage at lamp fb = 3v, r l = 0.2 0.4 v output high voltage at lamp fb = 2v, r l = 7.1 7.5 7.8 v source current voltage at lamp fb = 0v, lfb out = 7v, t a = 25c C0.05 C0.15 C0.25 ma sink current voltage at lamp fb = 5v, lfb out = 0.3v, t a = 25c 0.05 0.12 0.22 ma pfc voltage feedback amplifier (peao, pvfb/ovp) input bias current C0.3 C1.0 a small signal transconductance 35 65 105 w input voltage range C0.3 5.0 v output low voltage at pvfb = 3v, r l = 0.2 0.4 v output high voltage at pvfb = 2v, r l = 6.5 6.8 7.1 v source current voltage at pvfb/ovp = 0v, peao = 6v, t a = 25c C0.05 C0.15 C0.25 ma sink current voltage at pvfb/ovp = 3v, peao = 0.3v, t a = 25c 0.03 0.07 0.16 ma pfc current limit comparator (pifb) current-limit threshold C0.90 C1.05 C1.15 v propagation delay 100mv step and 100mv overdrive 100 ns oscillator initial accuracy t a = 25c 72 76 80 khz voltage stability v ccz C 4.5v < v cc ML4833cp ...................................................... 70c/w ML4833cs .................................................... 100c/w operating conditions temperature range ........................................0c to 85c w w
ML4833 4 rev. 1.0 10/12/2000 electrical characteristics (continued) parameter conditions min typ max units oscillator (continued) c t charging current voltage at lamp fb = 3v, r t /c t = 2.5v, r x /c x = 0.9v (preheat) C90 C110 C130 a lamp fb = 3v, r t /c t = 2.5v, r x /c x = open C180 C220 C260 a c t discharge current voltage at r t /c t = 2.5v 4.0 5.5 7.0 ma output drive deadtime 0.65 1 1.35 s reference section output voltage t a = 25c, i o = 1ma 7.4 7.5 7.6 v line regulation v ccz C 4.5v < v cc < v ccz C 0.5v 2 35 mv load regulation 1ma < i o < 5ma 2 15 mv temperature stability 0.4 % total variation line, load, temp 7.35 7.65 v output noise voltage 10hz to 10khz 50 v long term stability t j = 125c, 1000 hrs 5 mv preheat and interrupt timer (r x /c x where r x = 680ky, c x = 4.7f) initial preheat period 0.8 s subsequent preheat period 0.7 s start period 1.2 s interrupt period 5.7 s r x /c x charging current C24 C28 C33 a r x /c x open circuit voltage v cc < start-up threshold 0.4 0.7 1.0 v r x /c x maximum voltage 7.0 7.3 7.7 v input bias current voltage at c ramp = 1.2v 0.1 a preheat lower threshold 1.05 1.22 1.36 v preheat upper threshold 4.2 4.7 5.1 v interrupt recovery threshold 1.05 1.22 1.36 v start period end threshold 6.05 6.6 7.35 v interrupt input (interrupt) interrupt threshold 1.1 1.22 1.4 v input bias current 0.1 a r set voltage 2.4 2.5 2.6 v ovp comparator (pvfb/ovp) ovp threshold 2.63 2.73 2.83 v hysteresis 0.18 0.23 0.27 v propagation delay 1.4 s
ML4833 rev. 1.0 10/12/2000 5 electrical characteristics (continued) parameter conditions min typ max units outputs (out a, out b, pfc out) output voltage low i out = 20ma 0.1 0.2 v i out = 200ma 1.0 2.0 v output voltage high i out = C20ma v cc C 0.2 v cc C 0.1 v i out = C200ma v cc C 2.0 v cc C 1.0 v output voltage low in uvlo i out = 10ma, v cc < start-up threshold 0.2 v output rise/fall time c l = 1000pf 20 ns under-voltage lockout and bias circuits ic shunt protection voltage (v ccz )i cc = 15ma 14.2 15.0 15.8 v start-up current v cc - start-up threshold 0.34 0.48 ma operating current v cc = 12.5v, 5.5 8.0 ma voltage at lamp fb = 0v, lfb out = 2.3, pvfb/ovp = 2.3v pifb = open start-up threshold v cc C 1.2 v ccz C 1.0 v cc C 0.8 v shutdown threshold v cc C 5.3 v ccz C 4.8 v cc C 4.3 v shutdown temperature (t dwn ) (note 2) 130 c hysteresis (t dwn ) 30 c pdwn pdwn threshold 0.9 1.0 1.1 v note 1: limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. note 2: junction temperature.
ML4833 6 rev. 1.0 10/12/2000 functional description overview the ML4833 consists of peak current controlled continuous boost power factor front end section with a flexible ballast control section. start-up and lamp-out retry timing are controlled by the selection of external timing components, allowing for control of a wide variety of different lamp types. the ballast section controls the lamp power using frequency modulation (fm) with additional programmability provided to adjust the vco frequency range. this allows for the ic to be used with a variety of different output networks. figure 1 depicts a detailed block diagram of ML4833. power factor section the ML4833 power factor section is a peak current sensing boost mode pfc control circuit in which only voltage loop compensation is needed. it is simpler than a conventional average current control method. it consists of a voltage error amplifier, a current sense amplifier (no compensation is needed), an integrator, a comparator, and a logic control block. in the boost topology, power factor correction is achieved by sensing the output voltage and the current flowing through the current sense resistor. duty cycle control is achieved by comparing the integrated voltage signal of the error amplifier and the voltage across r sense . the duty cycle control timing is shown in figure 2. setting minimum input voltage for output regulation can be achieved by selecting c ramp according to equation 1. c peao k dts s p v vv l dts r ramp max out in out in sense =--m {} - - ? ? ? ? - ? ? 22 111 1 22 2 18 () . () (1) overvoltage protection and inhibit the ovp pin serves to protect the power circuit from being subjected to excessive voltages if the load should change suddenly (lamp removal). a divider from the high voltage dc bus sets the ovp trip level. when the voltage on pvfb/ovp exceeds 2.75v, the pfc transistor are inhibited. the ballast section will continue to operate. 6 r set r t /c t vcc v ref gnd 2.5v pvfb/ovp peao c ramp pifb 7 r x /c x 9 16 17 11 18 1 10 2 out b 13 + + + + + 2.5v 1.0v + 1.25v ?.0v 2.75v preheat timer osc clk under-voltage thermal shutdown refok + tq pgnd 12 out a 14 pfc out 15 pdwn 3 interrupt 8 lfb out 5 lamp fb 4 ovp i sense amplifier ilim r sq r s q v to i figure 1. ML4833 detailed block diagram
ML4833 rev. 1.0 10/12/2000 7 figure 2. ML4833 pfc controller section + + l a m p l a m p lamp network inverter ra sw2 l sw1 r sense sine rb v out emi filter 14 2 pifb c ramp c1 c2 r1 c ramp out a pvfb/ovp 18 ? s vref1 osc sine ramp clk pfc out clk rq v to i peao 10 peao 1 transconductance amplifiers the pfc voltage feedback amplifier is implemented as an operational transconductance amplifier. it is designed to have low small signal forward transconductance such that a large value of load resistor (r1) and a low value ceramic capacitor (<1f) can be used for ac coupling (c1) in the frequency compensation network. the compensation network shown in figure 3 will introduce a zero and a pole at: f rc f rc zp == 1 2 1 2 11 12 pp (2) + 18 2.5v pvfb/ovp r1 c1 c2 figure 3. compensation network
ML4833 8 rev. 1.0 10/12/2000 the oscillator frequency is determined by the following equations: f tt osc chg dis = + 1 (3) and trcin virv virv chg t t ref ch t tl ref ch t th = +- +- ? ? ? ? (4) the oscillators minimum frequency is set when i ch = 0 where: f rc osc tt @ 1 051 . (5) figure 4 shows the output configuration for the operational transconductance amplifiers. current mirror in out current mirror in out gmv in io = gmv in iq + 2 gmv in iq 2 figure 4. output configuration a dc path to ground or v cc at the output of the transconductance amplifiers will introduce an offset error. the magnitude of the offset voltage that will appear at the input is given by v os = io/gm. for an io of 1a and a gm of 0.05 w the input referred offset will be 20mv. capacitor c1 as shown in figure 3 is used to block the dc current to minimize the adverse effect of offsets. slew rate enhancement is incorporated into all of the operational transconductance amplifiers in the ML4833. this improves the recovery of the circuit in response to power up and transient conditions. the response to large signals will be somewhat non-linear as the transconductance amplifiers change from their low to high transconductance mode. this is illustrated in figure 5. v in differential linear slope region 0 i o figure 5. transconductance amplifier characteristics ballast output section the ic controls output power to the lamps via frequency modulation with non-overlapping conduction. this means that both ballast output drivers will be low during the discharging time t dis of the oscillator capacitor c t . oscillator the vco frequency ranges are controlled by the output of the lfb amplifier (r set ). as lamp current increases, lfb out falls in voltage, causing the c t charging current to increase, thereby causing the oscillator frequency to increase. since the ballast output network attenuates high frequencies, the power to the lamp will be decreased. 17 + 1.25/3.75 7 c t v ref i chg v ref control r t /c t r t 5.5ma clock c t v th = 3.75v v tl = 1.25v t dis t chg figure 6. oscillator block diagram and timing w
ML4833 rev. 1.0 10/12/2000 9 this assumes that t chg >> t dis . when lfb out is high, i ch = 0 and the minimum frequency occurs. the charging current varies according to two control inputs to the oscillator: 1. the output of the preheat timer 2. the voltage at lfb out (lamp feedback amplifier output) in preheat condition, charging current is fixed at i r chg preheat set () . = 25 (6) in running mode, charging current decreases as the voltage rises from 0v to v oh at the lamp fb amplifier. the highest frequency will be attained when i chg is highest, which is attained when voltage at lfb out is at 0v: i r chg set () 0 5 = (7) highest lamp power, and lowest output frequency are attained when voltage at lfb out is at its maximum output voltage (v oh ). in this condition, the minimum operating frequency of the ballast is set per equation 5 above. for the ic to be used effectively in dimming ballasts with higher q output networks a larger c t value and lower r t value can be used, to yield a smaller frequency excursion over the control range (voltage at lfb out). the discharge current is set to 5ma. assuming that i dis >> i rt : tc dis vco t () @ 600 (8) ic bias, under-voltage lockout and thermal shutdown the ic includes a shunt clamp which will limit the voltage at v cc to 15v (v ccz ). the ic should be fed with a current limited source, typically derived from the ballast transformer auxiliary winding. when v cc is below v ccz C 1.1v, the ic draws less than 0.48ma of quiescent current and the outputs are off. this allows the ic to start using a bleed resistor from the rectified ac line. to help reduce ballast cost, the ML4833 includes a temperature sensor which will inhibit ballast operation if the ics junction temperature exceeds 120c. in order to use this sensor in lieu of an external sensor, care should be taken when placing the ic to ensure that it is sensing temperature at the physically appropriate point in the ballast. the ML4833s die temperature can be estimated with the following equation: tt p cw jad @+ + (/) 65 (9) vccz v(on) v(off) 5.5ma 0.34ma v cc i cc t t figure 7. typical v cc and i cc waveforms when the ML4833 is started with a bleed resistor from the rectified ac line and bootstrapped from an auxiliary winding. starting, re-start, preheat and interrupt the lamp starting scenario implemented in the ML4833 is designed to maximize lamp life and minimize ballast heating during lamp out conditions. the circuit in figure 8 controls the lamp starting scenarios: filament preheat and lamp out interrupt. c x is charged with a current of i r(set) /4 and discharged through r x . the voltage at c x is initialized to 0.7v (v be ) at power up. the time for c x to rise to 4.8v is the filament preheat time. during that time, the oscillator charging current (i chg ) is 2.5/r set . this will produce a high frequency for filament preheat, but will not produce sufficient voltage to ignite the lamp or cause significant glow current. after cathode heating, the inverter frequency drops to f min causing a high voltage to appear to ignite the lamp. if lamp current is not detected when the lamp is supposed to have ignited, the lamp voltage feedback coming into pin 8 remains below 1.25v, the c x charging current is shut off and the inverter is inhibited until c x is discharged by r x to the 1.2v threshold. shutting off the inverter in this manner prevents the inverter from generating excessive heat when the lamp fails to strike or is out of socket. typically this time is set to be fairly long by choosing a large value of r x .
ML4833 10 rev. 1.0 10/12/2000 a summary of the operating frequencies in the various operating modes is shown below. operating mode operating frequency [f(max) to f(min)] preheat 2 dimming lock-out f(min) dimming control f(min) to f(max) 9 8 r x c x 6.8 + 1.2/4.8 heat inhibit 0.625 r set + 1.2/6.8 + 1.25v dimming lockout r x /c x interrupt q r s figure 8. lamp preheat and interrupt timers lfb out is ignored by the oscillator until c x reaches 6.8v threshold. the lamps are therefore driven to full power and then dimmed. the c x pin is clamped to about 7.5v. 6.8 4.8 1.2 .65 0 >1.25 r x /c x heat dimming lockout int inhibit figure 9. lamp starting and restart timing typical applications figure 10 shows a schematic for a dimming power-factor corrected 60w ballast, designed to operate two f32t8 fluorescent lamps connected in series.
ML4833 rev. 1.0 10/12/2000 11 figure 10. 220v dimming ballast r1 r5 c2 r24 r4 r8 r2 c9 c23 c8 violet remote manual dimmer 0?0vdc c3 r3 c22 r6 peao pifb pdwn lamp fb lfb out r set r t c t interrupt r x c x 1 2 3 4 5 6 7 8 9 pvfb v ref v cc pfc out out a out b pgnd gnd c ramp 18 17 16 15 14 13 12 11 10 u1 ML4833 d3 d1 d4 d5 d6 d10 d2 hot neutral f1 l1 l2 c2 c1 c3 c25 c20 c26 d9 d12 d13 t1 10 6 98 r20 r17 r18 r14 pdwn r4 c7 c24 r3 r25 r5 r15 r23 c11 c4 c6 c5 r10 r16 r22 c10 r8 r13 r12 r11 q1 d7 d11 d8 c13 c14 c16 c21 c12 c15 q2 q3 t2 6 72 3 1 56 10 8 1 c17 c19 r19 t4 tp4 6 7 4 3 2 1 9 8 r r y y b b r21 r2 r1 u1 c4 c1 220 vac tp2 tp3 tp1 tp5 t5 + + u2 3 8 7 1 2 5 6 r7 4 gray r6 q1 d2 d1 r7 t1 4 3 dimmer control interface subassembly +
ML4833 12 rev. 1.0 10/12/2000 physical dimensions inches (millimeters) seating plane 0.240 - 0.260 (6.09 - 6.61) pin 1 id 0.295 - 0.325 (7.49 - 8.26) 0.890 - 0.910 (22.60 - 23.12) 0.016 - 0.022 (0.40 - 0.56) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.015 min (0.38 min) 18 0o - 15o 1 0.050 - 0.065 (1.27 - 1.65) 0.170 max (4.32 max) 0.125 min (3.18 min) 0.045 min (1.14 min) (4 places) package: p18 18-pin pdip seating plane 0.291 - 0.301 (7.39 - 7.65) pin 1 id 0.398 - 0.412 (10.11 - 10.47) 0.449 - 0.463 (11.40 - 11.76) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.022 - 0.042 (0.56 - 1.07) 0.095 - 0.107 (2.41 - 2.72) 0.005 - 0.013 (0.13 - 0.33) 0.090 - 0.094 (2.28 - 2.39) 18 0.009 - 0.013 (0.22 - 0.33) 0o - 8o 1 0.024 - 0.034 (0.61 - 0.86) (4 places) package: s18 18-pin soic
ML4833 rev. 1.0 10/12/2000 13 ordering information part number temperature range package ML4833cp (end of life) 0c to 85c molded dip (p18) ML4833cs (obsolete) 0c to 85c soic (s18) life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ?2000 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

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